1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
Recently, techniques of increasing the channel mobility of a MIS transistor by providing strain to a channel region of the MIS transistor have been received much attention. As one of these techniques, proposed is a method in which a region for forming a source/drain region of a silicon substrate is etched to form a recessed portion, and an epitaxial SiGe layer is formed in the recessed portion (refer to U.S. Pat. No. 6,621,131). SiGe has a lattice constant larger than that of silicon, and thus an epitaxial SiGe layer can apply stress to a channel region. Therefore, strain is provided to a channel region, and the channel mobility of the MIS transistor is increased.
However, the above techniques have the following problems. The problems are explained with reference to FIG. 1 and FIGS. 2A and 2B. FIG. 1 is a plan view, FIG. 2A is a cross-sectional view taken along line A-A′ of FIG. 1, and FIG. 2B is a cross-sectional view taken along line B-B′ of FIG. 1.
In FIG. 1 and FIGS. 2A and 2B, reference numeral 111 denotes a silicon substrate, reference numeral 112 denotes an isolation region, reference numeral 113 denotes an epitaxial SiGe layer serving as a source/drain, reference numeral 114 denotes a gate structure formed of a gate insulating film (not shown), a gate electrode 115 and side wall spacers 116.
The epitaxial SiGe layer 113 is obtained by forming SiGe in a recessed portion formed in a silicon substrate by selective epitaxial growth. Under epitaxial growth conditions with high selectivity, the SiGe layer 113 is formed only on exposed surfaces of the silicon substrate 111. Therefore, as shown in FIG. 2A, the SiGe layer 113 is not formed on the side surfaces of the isolation regions 112, and a facet 113a is formed in the SiGe layer 113. As a result, a gap 117 is formed between the isolation region 112 and the epitaxial SiGe layer 113. With the gap 117, when a silicide is formed on the epitaxial SiGe layer 113, the silicide is formed also on the facet 113a. Since the silicide formed on the facet 113a is very close to the silicon substrate 111, it causes the problem of deterioration in junction leakage property. Further, the facet reduces an effective channel width, and thus also causes the problem of deterioration in the transistor property.
The above problems may be caused not only when an SiGe layer is formed in a recessed portion of a silicon substrate by epitaxial growth, but also when generally a semiconductor layer is formed in a recessed portion of a semiconductor substrate by epitaxial growth.
As described above, in prior art, there is the problem that properties of the transistor is deteriorated due to a facet formed in an epitaxial semiconductor portion when the epitaxial semiconductor portion is formed in a recessed portion of a semiconductor substrate (semiconductor element region).